The present invention relates to a semiconductor device and to a method of manufacturing the device. More particularly, it relates to a structure having an electrical connection to a semiconductor region having a shallow PN junction of, especially, a complementary MOS semiconductor device.
A shallow PN junction greatly contributes to the improvement in performances of semiconductor devices. For example, a bipolar transistor, of the type in which the base and emitter regions constitute a shallow PN junction, improves high frequency characteristics and current amplification factors. An insulated gate field effect transistor, in which the source and drain regions form shallow PN junctions, has an improved increase of its mutual conductance and increment of integration degree of circuit elements.
However, it is well known that when a metal electrode (wiring), especially, of aluminum, is provided to make an ohmic contact with a semiconductor region forming the shallow PN junction, the PN junction is easily destroyed by the metal electrode (wiring) with a resulting of short circuit between two semiconductor regions forming the PN junction. Specifically, in the manufacturing step of the metal electrode, the aluminum is deposited on the semiconductor region. Then a heat treatment (at a temperature from 400.degree. C. to 500.degree. C.) is performed in order to ensure the mutual electrical condition. By this heat treatment, aluminum diffuses into the semiconductor region while semiconductor material diffuses into the aluminum. As the result of this mutual diffusion, an alloy material of the semiconductor material and aluminum is formed to enhance the electrical connection of the semiconductor region and the aluminum wiring. This alloy material grows toward the PN junction, from the contact portion between the semiconductor region and the metal wire. The growth of the alloy material advances as a function of the heat treatment time. When the PN junction is relatively deep, the alloy material does not reach the PN junction and does not destroy it. However, when the PN junction is very shallow, for example, 0.5.mu., the alloy reaction of the semiconductor region and the metal wire advances near the PN junction to increase a leakage current at the PN junction, and finally reaches the PN junction to destroy it. This destruction alloy is the so-called "alloy spike" .
The conventional methods have been used for providing the electrode contact to the shallow PN junction, and for overcoming the above-mentioned disadvantages. When the semiconductor material is silicon, these methods are as follows:
(i) An aluminum layer containing silicon in an amount above its solid solubility limitation at a room temperature is deposited on an impurity region of a silicon substrate. Thus, the reaction of aluminum with silicon is carried out so as not to reach the PN junction, as disclosed in U.S. Pat. No. 3,382,568 issued on May 14, 1968 and granted to L. L. Kuiper.
(ii) An additional silicon layer is layered between the impurity region and the aluminum layer, and silicon diffused into the aluminum layer is not supplied from the impurity region but is supplied from the additional silicon layer, as is also disclosed in the above cited Kuiper reference;
(iii) A polycrystalline silicon layer, doped with an impurity, is deposited on a monocrystalline silicon substrate. Then, the impurity is diffused into the monocrystalline silicon substrate to form the impurity region having a shallow PN junction. The aluminum wiring layer is deposited on poly-crystalline silicon layer to be electrically connected to the impurity region.
By the above methods, the aluminum wiring layer has been formed for the semiconductor region having the shallow PN junction.
The formation of wiring (electrode) connected to the semiconductor region is generally performed in such a manner that, wiring material is deposited on a semiconductor region through a contact window. The contact window is formed after an insulating layer for protecting the surface of the semiconductor body and the PN junction reaching the surface is etched away at its predetermined location. The formation of the contact window in the insulating layer is performed by a photoetching technique, which is well known. In addition, the semiconductor region is also formed by using a diffusing mask having a window at its predetermined location, which mask is formed by the photoetching technique.
Ideally, it is preferred that those contact windows should be precisely formed at desired locations and with desired size. However, because the misalignment of mask patterns for forming the contact window is unavoidable, the contact window and the window through which diffussion occurs are formed in practice at locations and in sizes which take into account the misalignment of the mask pattern. Consequently, the diffused region and contact windows which are actually formed become larger than ideal. Furthermore, by taking account of the possible misalignment of the mark pattern, the distance between the adjacent regions or elements is elongated. These problems are inherent to the photoetching method, and due to these problem, the increase of an integration density of circuit elements is impossible.
The above conventional methods have succeeded in an attempt to avoid the breakdown of the shallow PN junction by the alloy spike, but have failed to increase the integration density due to the above problems in the photoetching method. More particularly, in the above methods (i) and (ii), the factor of the mask misalignment is already considered in the course of design, so that the contact window for the electrode connection is located on only one conductivity type semiconductor region. However, in such a design, if the misalignment of the mask pattern is neglected to increase the integration density is the contact window often exposes the PN junction. As a result of such a junction exposure, in forming the aluminum layer containing silicon or in successively forming the silicon layer and the aluminum layer, a shortcircuiting of the PN junction would occur irrespective of the alloy spike.
The method (iii) is that the semiconductor region is formed by the impurity diffusion from the poly-crystalline silicon layer containing the impurity. The aluminum interconnecting layer is deposited on the doped poly-crystalline silicon layer. Accordingly, on the poly-crystalline silicon layer is formed on a semiconductor region and both are of the same conductivity type. Therefore, there is neither the breakdown of the PN junction by the alloy spike nor the shortcircuiting by the interconnecting material. However, the formation of the semiconductor region by the impurity diffusion from the doped poly-crystalline silicon layer is not compatible with the mass production of semiconductor devices. This is because the method has such a disadvantage that the impurity profile and the junction depth cannot be precisely controlled.
Furthermore, the aluminum layer makes direct contact with the polycrystalline silicon layer containing the impurity. In this case, completely different kinds of two materials are in contact, and therefore the contact intimacy between them is poor. Even if the heat treatment is performed, a reaction between them hardly takes place. This is because a sufficient amount of the impurity is already doped in the poly-crystalline silicon layer so that there is almost no the diffusion of aluminum in to the poly-crystalline silicon. Accordingly, when the semiconductor devices formed by the method (iii) are subjected to the heating cycle, a thermal stress is applied to the aluminum layer, so that the aluminum layer peels off the poly-crystalline silicon layer due to the poor contact force. In an extreme case, a wiring of the aluminum layer is broken.
The present invention will be described hereinafter, in which a term "non-doped semiconductor layer or region" is defined as a semiconductor layer or region into which impurities are not intentionally doped. Similarly, a term "a non-doped poly-crystalline silicon layer" means a poly-crystalline silicon layer into which impurities are not intentionally doped. That is, no impurity is doped into them by the diffusion method, the ion implantation or the like. However, the non-doped semiconductor and poly-crystalline silicon layer or region include ones doped with impurities which exist in ambient atmosphere or which exist on the object on which they are formed.